Formal Verification of Hardware Design
Formal Verification of Hardware Design
Quantifying Design Quality Through Design Experiments
IEEE Design & Test
Fault-simulation based design error diagnosis for sequential circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
High-level design verification of microprocessors via error modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Logic Design Validation via Simulation and Automatic Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
A Fault Tolerant Approach to Microprocessor Design
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
Using fault sampling to compute I/sub DDQ/ diagnostic test sets
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Using ATPG for clock rules checking in complex scan designs
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
EXPLOITING DON'T CARES TO ENHANCE FUNCTIONAL TESTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Identifying Redundant Gate Replacements in Verification by Error Modeling
ITC '01 Proceedings of the 2001 IEEE International Test Conference
ErrorTracer: A Fault Simulation-Based Approach to Design Erorr Diagnosis
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Design Verification by Test Vectors and Arithmetic Transform Universal Test Set
IEEE Transactions on Computers
An efficient evaluation and vector generation method for observability-enhanced statement coverage
Journal of Computer Science and Technology
Journal of Electronic Testing: Theory and Applications
Architecting a reliable CMP switch architecture
ACM Transactions on Architecture and Code Optimization (TACO)
| Hi-index | 0.00 |
We present a simulation-based method for combinational design verification that aims at complete coverage of specified design errors using conventional ATPG tools. The error models used in prior research are examined and reduced to four types: gate substitution errors (GSEs), gate count errors (GCEs), input count errors (ICEs), and wrong input errors (WIEs). Conditions are derived for a gate to be completely testable for GSEs; These conditions lead to small test sets for GSEs. Near-minimal test sets are also derived for GCEs. We analyze redundancy in design errors and relate this to single stuck-line (SSL) redundancy. We show how to map all the foregoing error types into SSL faults, and describe an extensive set of experiments to evaluate the proposed method. Our experiments demonstrate that high coverage of the modeled design errors can be achieved with small test sets.