Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Locating functional errors in logic circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Differential fault simulation - a fast method using minimal memory
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Locating logic design errors via test generation and don't-care propagation
EURO-DAC '92 Proceedings of the conference on European design automation
Error diagnosis for transistor-level verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Logic synthesis for engineering change
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Design verification via simulation and automatic test pattern generation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A method for automatic design error location and correction in combinational logic circuits
Journal of Electronic Testing: Theory and Applications
The use of random simulation in formal verification
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Design error diagnosis in sequential circuits
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis
Proceedings of the IEEE International Test Conference
A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
On correction of multiple design errors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiple error diagnosis based on xlists
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A Domain Coverage Metric for the Validation of Behavioral VHDL Descriptions
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Validation Fault Model for Timing-Induced Functional Errors
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Error traces in model-based debugging of hardware description languages
Proceedings of the sixth international symposium on Automated analysis-driven debugging
Automated Source-Level Error Localization in Hardware Designs
IEEE Design & Test
Employing test suites for verilog fault localization
CAEPIA'09 Proceedings of the Current topics in artificial intelligence, and 13th conference on Spanish association for artificial intelligence
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This paper addresses the problem of locating design errors in a sequential circuit. For single-error circuits, we consider a signal ƒ as a potential error source only if the circuit can be completely rectified by re-synthesizing ƒ (i.e., changing the function of signal ƒ). In order to handle larger circuits, we do not rely on Binary Decision Diagram. Instead, we search for potential error sources by a modified sequential fault simulation process. The main contributions of this paper are two-fold: (1) we derive the necessary and sufficient condition of whether an erroneous input sequence (i.e., an input sequence producing erroneous responses) can be corrected by changing the function of a particular internal signal; and (2) we propose a modified fault simulation procedure to check this condition. Our approach does not rely on any error model, and thus, is suitable for general types of errors. Furthermore, it can be easily extended to identify multiple errors. Experimental results on ISCAS89 benchmark circuits are presented to demonstrate its capability.