Digital logic testing and simulation
Digital logic testing and simulation
Split circuit model for test generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Quality level and fault coverage for multichip modules
DAC '83 Proceedings of the 20th Design Automation Conference
LSI product quality and fault coverage
DAC '81 Proceedings of the 18th Design Automation Conference
Algorithms for fast, memory efficient switch-level fault simulation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Sequential circuit fault simulation by fault information tracing algorithm: FIT
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
On efficient concurrent fault simulation for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Fast hierarchical multi-level fault simulation of sequential circuits with switch-level accuracy
DAC '93 Proceedings of the 30th international Design Automation Conference
On Fault Simulation for Synchronous Sequential Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
DAC '96 Proceedings of the 33rd annual Design Automation Conference
New methods for parallel pattern fast fault simulation for synchronous sequential circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
New methods of improving parallel fault simulation in synchronous sequential circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Fault-simulation based design error diagnosis for sequential circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
A switch level fault simulation environment
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Overhead reduction techniques for hierarchical fault simulation
ATS '95 Proceedings of the 4th Asian Test Symposium
Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
ErrorTracer: A Fault Simulation-Based Approach to Design Erorr Diagnosis
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Extraction of Schematic Array Models for Memory Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Parallel fault backtracing for calculation of fault coverage
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Parallel X-fault simulation with critical path tracing technique
Proceedings of the Conference on Design, Automation and Test in Europe
Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A new, fast fault simulator called differential fault simulator, DSIM, for sequential circuits is described. Unlike the concurrent fault simulation, DSIM simulates each machine by simulating its machine differences from the other machine just simulated instead of simulating its input differences from the previous status of the same machine. In this manner, DSIM simulates each machine (good or bad) separately for every test vector. Therefore, DSIM dramatically reduces the dynamic memory requirement and the overhead in the memory management in the concurrent fault simulation. Also unlike the single fault propagation which simulates each bad machine by simulating its machine difference from the good machine, the overhead to restore the good machine status before each bad machine simulation is eliminated in DSIM. Our experiments show that DSIM runs 3-12 times faster than an existing concurrent fault simulator and an experimental single fault propagation simulator. Furthermore, owing to the straightforward operations, DSIM is very easy to implement and maintain. Implementation consists of less than 300 lines of “C” language statements added to the event-driven true-value simulator in an existing sequential test generation system, STG. Currently DSIM uses a zero-delay timing model, while inclusion of other delay models is under development.