COSMOS: a compiled simulator for MOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Differential fault simulation - a fast method using minimal memory
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Algorithms for fast, memory efficient switch-level fault simulation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor
Proceedings of the IEEE International Test Conference on Test and Design Validity
Logic Verification of Very Large Circuits Using Shark
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
VOSS - A Formal Hardware Verification System User''s Guide
VOSS - A Formal Hardware Verification System User''s Guide
Proceedings of the 40th annual Design Automation Conference
Emulating switch-level models of CMOS circuits
Microelectronic Engineering
Fault injection into Verilog models for dependability evaluation of digital systems
ISPDC'03 Proceedings of the Second international conference on Parallel and distributed computing
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This paper presents a fault simulation environment which accepts pure switch level or mixed switch/RT level descriptions of the design under test. Switch level fault injection strategies for the stuck-at, transition and logic bridge models are presented. A fault simulation algorithm is presented, along with design issues and optimizations. The fault simulation algorithm places no restrictions on the circuit styles used to implement designs. Mixed level simulation issues are discussed. Fault simulation performance numbers on large industrial benchmarks are reported.