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Microelectronic Engineering
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In this paper, we will present Shark, a software based logic verification technology that achieves high-performance switch-level simulations on multi-million transistor circuits. Prior to Shark, logic verification (LVR) of multi-million transistor circuits relied on hardware emulators which are extremely expensive and are captive solutions that do not scale well, resulting in custom "one-time" solutions.Shark leverages general-purpose workstations to perform LVR and achieves high performance simulations on very large circuits through three key technologies: 1) a circuit partitioner based on latch boundary components, design hierarchy driven clustering, and latch/activity based load balancing, 2) a high-performance switch-level simulator capable of simulating very large models and run word-parallel simulations, and 3) a simulation backplane that can connect an arbitrary number of simulators to form a distributed/parallel simulation environment using a synchronous communication model.Shark is the only software switch-level LVR solution we know of that can scale to very large designs and match, if not exceed, the simulation performance of hardware emulators. Shark has been tested on circuits of up to 15M transistors. Our results show that the partitioner scales linearly with circuit size in both runtime and memory usage. More importantly, the partitioning strategy produces near linear simulation performance improvement with the number of partitions. On an Intel circuit with about 5M transistors, Shark achieved a simulation throughput of 19 Hz.This new technology presents a cost-effective and practical alternative to hardware emulation solutions. Shark addresses the logic verification problem of very large circuits at a fraction of the cost and is designed as a scalable solution for all future logic verification needs.