ACM Transactions on Programming Languages and Systems (TOPLAS)
Characterization of parallelism and deadlocks in distributed digital logic simulation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Ravel: assigned-delay compiled-code logic simulation
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
A general method for compiling event-driven simulations
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Actor based parallel VHDL simulation using time warp
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Parallel algorithms for VHDL simulation
Parallel algorithms for VHDL simulation
Maintaining knowledge about temporal intervals
Communications of the ACM
Asynchronous distributed simulation via a sequence of parallel computations
Communications of the ACM - Special issue on simulation modeling and statistical computing
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Logic Synthesis Using Synopsys
Logic Synthesis Using Synopsys
Computer Architecture; A Quantitative Approach
Computer Architecture; A Quantitative Approach
Hardware Design and Simulation in Val-VHDL
Hardware Design and Simulation in Val-VHDL
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Process combination to increase event granularity in parallel logic simulation
IPPS '95 Proceedings of the 9th International Symposium on Parallel Processing
Logic Verification of Very Large Circuits Using Shark
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
A New Algorithm for VHDL Parallel Simulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 14.99 |
In this paper, we present approaches and algorithms for parallelization of compiled event driven VHDL simulations on shared-memory multiprocessors (SMP). An efficient single-threaded algorithm for simulation of VHDL descriptions is first presented. This algorithm is shown to be competitive with a commercial VHDL simulator. Schemes for multithreaded execution of this algorithm are then described. These have been implemented on top of the POSIX pthreads library and experimental results have been shown on a Sun SparcServer 1000E. Speedups of up to four on eight processors have been achieved for some benchmarks.