ACM Transactions on Programming Languages and Systems (TOPLAS)
Nearest-neighbor mapping of finite element graphs onto processor meshes
IEEE Transactions on Computers
Parallel discrete event simulation
WSC '89 Proceedings of the 21st conference on Winter simulation
Corolla partitioning for distributed logic simulation of VLSI-circuits
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
Evaluating the use of pre-simulation in VLSI circuit partitioning
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
A static partitioning and mapping algorithm for conservative parallel simulations
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
Asynchronous distributed simulation via a sequence of parallel computations
Communications of the ACM - Special issue on simulation modeling and statistical computing
Parallel Simulated Annealing using Speculative Computation
IEEE Transactions on Parallel and Distributed Systems
Concurrency preserving partitioning (CPP) for parallel logic simulation
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Conservative circuit simulation on shared-memory multiprocessors
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Actor based parallel VHDL simulation using time warp
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Improving conservative VHDL simulation performance by reduction of feedback
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Parallel compiled event driven VHDL simulation
ICS '98 Proceedings of the 12th international conference on Supercomputing
Partitioning WCN models for parallel simulation of radio resource management
Wireless Networks - Special issue: Design and modeling in mobile and wireless systsems
Automatic Parallelization of Compiled Event Driven VHDL Simulation
IEEE Transactions on Computers
Load Balancing and Workload Minimization Of Overlapping Parallel Tasks
ICPP '97 Proceedings of the international Conference on Parallel Processing
A parallel logic simulation framework: study, implementation, and performance
SpringSim '10 Proceedings of the 2010 Spring Simulation Multiconference
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Distributing computation among multiple processors is one approach to reducing simulation time for large VLSI circuit designs. However, parallel simulation introduces the problem of how to partition the logic gates and system behaviors of the circuit among the available processors in order to obtain maximum speedup. A complicating factor that is often ignored is the effect of the time-synchronization protocol (conservative [1] or optimistic [2]). Inherent in the partitioning problem is the question of how to effectively measure the relative quality of a partition. This paper describes an objective cost function for measuring the relative quality of a task partition that includes a synchronization factor for a conservative NULL-message protocol. A graph-based partitioning tool based on this cost function is used to perform the static task allocation for parallel simulation of a structural VHDL circuit. Results for two 1000 – 4000 gate circuits demonstrate that the additional consideration of the synchronization protocol in the cost function generates partitions that exhibit improved speedup.