ACM Transactions on Programming Languages and Systems (TOPLAS)
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Effect of communication overheads on Time Warp performance: an experimental study
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
A static partitioning and mapping algorithm for conservative parallel simulations
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
Parallel logic level simulation of VLSI circuits
WSC '94 Proceedings of the 26th conference on Winter simulation
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
Parallel gate-level circuit simulation on shared memory architectures
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
Dynamic load balancing of a multi-cluster simulator on a network of workstations
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
Parallel logic simulation of VLSI systems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Concurrency preserving partitioning (CPP) for parallel logic simulation
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Conservative circuit simulation on shared-memory multiprocessors
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Partitioning of VLSI circuits and systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Parallel and distributed discrete event simulation: algorithms and applications
WSC '93 Proceedings of the 25th conference on Winter simulation
A multidimensional study on the feasibility of parallel switch-level circuit simulation
Proceedings of the eleventh workshop on Parallel and distributed simulation
Analysis and simulation of mixed-technology VLSI Systems
Journal of Parallel and Distributed Computing - Parallel and Distributed Discrete Event Simulation--An Emerging Technology
An adaptive partitioning algorithm for distributed discrete event simulation systems
Journal of Parallel and Distributed Computing - Problems in parallel and distributed computing: Solutions based on evolutionary paradigms
A parallel logic simulation framework: study, implementation, and performance
SpringSim '10 Proceedings of the 2010 Spring Simulation Multiconference
Robust partitioning for hardware-accelerated functional verification
Proceedings of the 48th Design Automation Conference
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Time Warp has evolved to a common technique for distributed simulation. Speedup in Time Warp simulation systems mainly depends on two overhead factors: first, the load on the simulators has to be well balanced and second, communication and rollbacks have to be kept to a minimum. Both of these factors are influenced by the partitioning of the simulated system. In this paper, we focus on various static partitioning schemes used to partition digital circuits for distributed simulation.A new hierarchical partitioning approach is presented, compared and rated with other partitioning schemes by evaluating benchmark circuits. Partitioning is done in two steps: a fine grained clustering step based on corollas and a coarse grained step forming partitions using the connectivity matrix. The corolla approach yields very good partitioning results even for a large number of partitions. The achieved speedups are almost linear (up to 12 partitions for larger circuits), as long as the partition sizes are large enough so that communication between the simulators is not a bottleneck. The results reveal the great impact of partitioning on the acceleration of distributed logic simulation and show the effectiveness of the presented corolla partitioning scheme.