Self-adjusting binary search trees
Journal of the ACM (JACM)
ACM Transactions on Programming Languages and Systems (TOPLAS)
Parallel discrete event simulation
Communications of the ACM - Special issue on simulation
The Stanford Dash Multiprocessor
Computer
SPLASH: Stanford parallel applications for shared-memory
ACM SIGARCH Computer Architecture News
Parallelism analyzers for parallel discrete event simulation
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Corolla partitioning for distributed logic simulation of VLSI-circuits
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
Highly parallel computing (2nd ed.)
Highly parallel computing (2nd ed.)
Understanding supercritical speedup
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
A static partitioning and mapping algorithm for conservative parallel simulations
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
Partitioning for synchronous parallel simulation
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
ANSS '91 Proceedings of the 24th annual symposium on Simulation
Asynchronous distributed simulation via a sequence of parallel computations
Communications of the ACM - Special issue on simulation modeling and statistical computing
SIMULATION OF PACKET COMMUNICATION ARCHITECTURE COMPUTER SYSTEMS
SIMULATION OF PACKET COMMUNICATION ARCHITECTURE COMPUTER SYSTEMS
Parallel logic simulation: an evaluation of centralized-time and distributed-time algorithms
Parallel logic simulation: an evaluation of centralized-time and distributed-time algorithms
Shared memory implementation of a parallel switch-level circuit simulator
PADS '98 Proceedings of the twelfth workshop on Parallel and distributed simulation
Support for Efficient Programming on the SB-PRAM
International Journal of Parallel Programming
Conservative Circuit Simulation on Multiprocessor Machines
HiPC '00 Proceedings of the 7th International Conference on High Performance Computing
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We investigate conservative parallel discrete event simulations for logical circuits on shared-memory multiprocessors. For a first estimation of the possible speedup, we extend the critical path analysis technique by partitioning strategies. To incorporate overhead due to the management of data structures, we use a simulation on an ideal parallel machine (PRAM). This simulation can be directly executed on the SB-PRAM prototype, yielding both an implementation and a basis for data structure optimizations. One of the major tools to achieve these is the SB-PRAM's hardware support for parallel prefix operations. Our reimplementation of the PTHOR program on the SB-PRAM yields substantially higher speedups than before.