Multiple-Way Network Partitioning
IEEE Transactions on Computers
Parallel architectural simulations on shared-memory multiprocessors
Parallel architectural simulations on shared-memory multiprocessors
Parallel discrete event simulation on shared-memory multiprocessors
ANSS '91 Proceedings of the 24th annual symposium on Simulation
Parallel mixed-level simulation of digital circuits using virtual time
Parallel mixed-level simulation of digital circuits using virtual time
Parallel logic simulation: an evaluation of centralized-time and distributed-time algorithms
Parallel logic simulation: an evaluation of centralized-time and distributed-time algorithms
Conservative circuit simulation on shared-memory multiprocessors
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Parallel logic simulation on a network of workstations using parallel virtual machine
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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A new partitioning method for synchronous PDES simulations is proposed. The method exploits characteristics of both the simulation method and of the application domain to arrive at efficient partitionings. A performance study shows that the method outperforms existing partitioning methods in terms of four different performance metrics.