Constructing test cases for partitioning heuristics
IEEE Transactions on Computers
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
A proper model for the partitioning of electrical circuits
DAC '72 Proceedings of the 9th Design Automation Workshop
A class of min-cut placement algorithms
DAC '77 Proceedings of the 14th Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Generalization of Min-Cut Partitioning to Tree Structures and its Applications
IEEE Transactions on Computers
A general purpose multiple way partitioning algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
On a parallel partitioning technique for use with conservative parallel simulation
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
High performance parallel logic simulations on a network of workstations
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
An efficient method of partitioning circuits for multiple-FPGA implementation.
DAC '93 Proceedings of the 30th international Design Automation Conference
Cost minimization of partitions into multiple devices
DAC '93 Proceedings of the 30th international Design Automation Conference
Geometric embeddings for faster and better multi-way netlist partitioning
DAC '93 Proceedings of the 30th international Design Automation Conference
Spectral K-way ratio-cut partitioning and clustering
DAC '93 Proceedings of the 30th international Design Automation Conference
Multiple-Way Network Partitioning with Different Cost Functions
IEEE Transactions on Computers
Evaluating the use of pre-simulation in VLSI circuit partitioning
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
Efficient network flow based min-cut balanced partitioning
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Multi-way VLSI circuit partitioning based on dual net representation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DAC '94 Proceedings of the 31st annual Design Automation Conference
Multi-way partitioning via spacefilling curves and dynamic programming
DAC '94 Proceedings of the 31st annual Design Automation Conference
Acyclic multi-way partitioning of Boolean networks
DAC '94 Proceedings of the 31st annual Design Automation Conference
EURO-DAC '94 Proceedings of the conference on European design automation
Distributed simulation for structural VHDL netlists
EURO-DAC '94 Proceedings of the conference on European design automation
Logic partition orderings for multi-FPGA systems
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Partitioning for synchronous parallel simulation
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
Assignment of cells to switches in PCS networks
IEEE/ACM Transactions on Networking (TON)
A gradient method on the initial partition of Fiduccia-Mattheyses algorithm
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Min-Cut Partitioning on Underlying Tree and Graph Structures
IEEE Transactions on Computers
Network partitioning into tree hierarchies
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A Hypergraph Framework for Optimal Model-Based Decomposition ofDesign Problems
Computational Optimization and Applications
A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A hierarchy-driven FPGA partitioning method
DAC '97 Proceedings of the 34th annual Design Automation Conference
Network flow based multi-way partitioning with area and pin constraints
Proceedings of the 1997 international symposium on Physical design
Partitioning-based standard-cell global placement with an exact objective
Proceedings of the 1997 international symposium on Physical design
On multilevel circuit partitioning
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Multiway partitioning with pairwise movement
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Greedy, Prohibition, and Reactive Heuristics for Graph Partitioning
IEEE Transactions on Computers
A probabilistic multicommodity-flow solution to circuit clustering problems
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Iterative improvement based multi-way netlist partitioning for FPGAs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Multilevel cooperative search: application to the circuit/hypergraph partitioning problem
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Timing-driven placement for hierarchical programmable logic devices
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Multi-way partitioning using bi-partition heuristics
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
IEEE Micro
A Fast and Robust Network Bisection Algorithm
IEEE Transactions on Computers
An adaptive partitioning algorithm for distributed discrete event simulation systems
Journal of Parallel and Distributed Computing - Problems in parallel and distributed computing: Solutions based on evolutionary paradigms
Optimality, scalability and stability study of partitioning and placement algorithms
Proceedings of the 2003 international symposium on Physical design
Dynamic Iterative Method for Fast Network Partitioning
HPCN Europe 2000 Proceedings of the 8th International Conference on High-Performance Computing and Networking
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Some Issues in Design of Distributed Deductive Databases
VLDB '94 Proceedings of the 20th International Conference on Very Large Data Bases
Interactive Partitioning (System Demonstration, Short)
GD '00 Proceedings of the 8th International Symposium on Graph Drawing
Adaptive delay estimation for partitioning-driven PLD placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Architecture driven k-way partitioning for multichip modules
EDTC '95 Proceedings of the 1995 European conference on Design and Test
When clusters meet partitions: new density-based methods for circuit decomposition
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Modifying Min-Cut for Hardware and Software Functional Partitioning
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
A new fuzzy-clustering-based approach for two-way circuit partitioning
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Multi-way partitioning of VLSI circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Distributed Diagnostic Simulation of Stuck-At Faults in Sequential Circuits
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
An Evaluation of Move-Based Multi-Way Partitioning Algorithms
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Integration, the VLSI Journal
Teramac-configurable custom computing
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
An improved circuit-partitioning algorithm based on min-cut equivalence relation
Integration, the VLSI Journal
Recursive bi-partitioning of netlists for large number of partitions
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Stable Multiway Circuit Partitioning for ECO
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Evolutionary Computation - Special issue on magnetic algorithms
Iterative-improvement-based declustering heuristics for multi-disk databases
Information Systems
Geometric crossover for multiway graph partitioning
Proceedings of the 8th annual conference on Genetic and evolutionary computation
IEEE Transactions on Parallel and Distributed Systems
Heuristics for scheduling file-sharing tasks on heterogeneous systems with distributed repositories
Journal of Parallel and Distributed Computing
A PROBE-Based Heuristic for Graph Partitioning
IEEE Transactions on Computers
Geometric crossovers for multiway graph partitioning
Evolutionary Computation
Autonomic hierarchical reconfiguration for wireless access networks
Journal of Network and Computer Applications
Hypergraph Cuts & Unsupervised Representation for Image Segmentation
Fundamenta Informaticae
Evaluating the Kernighan-Lin Heuristic for Hardware/Software Partitioning
International Journal of Applied Mathematics and Computer Science
Scheduling of tasks with batch-shared I/O on heterogeneous systems
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Graph partitioning strategies for efficient BFS in shared-nothing parallel systems
WAIM'10 Proceedings of the 2010 international conference on Web-age information management
Multi-FPGA partitioning method based on topological levelization
Journal of Electrical and Computer Engineering
Genetic approaches for graph partitioning: a survey
Proceedings of the 13th annual conference on Genetic and evolutionary computation
Weighted adaptive neighborhood hypergraph partitioning for image segmentation
ICAPR'05 Proceedings of the Third international conference on Pattern Recognition and Image Analysis - Volume Part II
A segmentation algorithm for noisy images
CAIP'05 Proceedings of the 11th international conference on Computer Analysis of Images and Patterns
Quotient geometric crossovers and redundant encodings
Theoretical Computer Science
Netlist bipartitioning using particle swarm optimisation technique
International Journal of Artificial Intelligence and Soft Computing
A high-performance triple patterning layout decomposer with balanced density
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 15.00 |
A multiple-block network partitioning algorithm adapted from a two-block iterative improvement partitioning algorithm is presented. This adaptation of the algorithm and of the level gain concept to multiple blocks seeks to improve the partition uniformly with respect to all blocks as oppose to making repeated uses of two-way partitioning. Appropriate data structures and a complexity analysis are presented, as well as experimental results. The experiments indicate that the optimal number of levels to use depends on the number of blocks and the net size and degree distributions of the network, but it varies little with the size of the network. In particular, higher levels are increasingly useful as the number of blocks in the partition increases. Theoretical results agree with the experimental results and form the basis for a predictor which, given a network and the desired number of blocks, approximates the optimal number of levels.