Performance-Driven Layer Assignment by Integer Linear Programming and Path-Constrained Hypergraph Partitioning

  • Authors:
  • C.-J. Shi;A. Vannelli;J. Vlach

  • Affiliations:
  • Department of Electrical and Computer Engineering, University of Iowa, Iowa City, Iowa 52242, U.S.A.;Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, Canada N2L 3G1;Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, Canada N2L 3G1

  • Venue:
  • Journal of Heuristics
  • Year:
  • 1997

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Abstract

Performance-driven physical layout design is becoming increasinglyimportant for both high speed integrated circuits and printed circuitboards. This paper studies the problem of assigning wire segments into twolayers so as to minimize the number of vias, while taking into accountperformance constraints such as layer preference and circuit timing. Weshow that using the Elmore delay model, three timing problems insynchronous digital circuits—the long path problem, the short pathproblem and the time skew problem—can be formulated as a set oflinear inequalities. We use the model of signed hypergraph to representtwo-layer routings and formulate the performance-driven optimum layerassignment problem as the path-constrained maximum balance problem in asigned hypergraph. Two solution methods are developed and implemented.First, an integer linear programming formulation is derived for findingexact solutions. Second, a local-search heuristic for hypergraphpartitioning is extended to cope with path-inequality constraints.Experimental results on a set of layer-assignment benchmarks demonstratedthat the path-constrained local-search heuristic achieves optimum ornear-optimum solutions with several orders of magnitude faster than theinteger linear programming approach.