Hierarchical timing verification system
Computer-Aided Design
A path selection algorithm for timing analysis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
ACTAS: an accurate timing analysis system for VLSI
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Development of a timing analysis program for multiple clocked network
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
SCAT—a new statistical timing verifier in a silicon compiler system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An accuration delay modeling technique for switch-level timing verification
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An effective delay analysis system for a large scale computer design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Plug-in timing models for an abstract timing verifier
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Hierarchical design verification for large digital systems
DAC '81 Proceedings of the 18th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Developments in logic network path delay analysis
DAC '82 Proceedings of the 19th Design Automation Conference
An efficient parallel critical path algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Incremental techniques for the identification of statically sensitizable critical paths
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A polynomial-time heuristic approach to approximate a solution to the false path problem
DAC '93 Proceedings of the 30th international Design Automation Conference
Delay and area optimization for compact placement by gate resizing and relocation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
An Efficient Critical Path Tracing Algorithm for Designing HighPerformance Vlsi Systems
Journal of Electronic Testing: Theory and Applications
Fast statistical timing analysis handling arbitrary delay correlations
Proceedings of the 41st annual Design Automation Conference
Efficient static timing analysis and applications using edge masks
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Low Power Oriented CMOS Circuit Optimization Protocol
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Statistical static timing analysis: A survey
Integration, the VLSI Journal
Statistical analysis of circuit timing using majorization
Communications of the ACM - A Blind Person's Interaction with Technology
Proceedings of the 16th Asia and South Pacific Design Automation Conference
NBTI-aware circuit node criticality computation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Sensitization criterion for threshold logic circuits and its application
Proceedings of the International Conference on Computer-Aided Design
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Path extracting algorithms are a very important part of timing analysis approach. In this paper we designed and developed several algorithms which can generate the K most critical paths in a non-increasing order of their delays. The effectiveness of these algorithms is shown by some experimental results.