DAC '83 Proceedings of the 20th Design Automation Conference
A timing verification system based on extracted MOS/VLSI circuit parameters
DAC '81 Proceedings of the 18th Design Automation Conference
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
Worst-case delay estimation of transistor groups
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
AWEsim: asymptotic waveform evaluation for timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for extracting the K most critical paths in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Timing analysis in a logic synthesis environment
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
WTA: waveform-based timing analysis for deep submicron circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
SLOCOP-II: a versatile timing verification system for MOSVLSI
EURO-DAC '90 Proceedings of the conference on European design automation
SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits
EURO-DAC '91 Proceedings of the conference on European design automation
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A new delay modeling technique for accurate timing verification of digital MOS circuits is presented. The technique is based on the ELogic approach and provides the user with a continuous speed-accuracy trade-off in addition to more accurate timing information than available with existing switch-level timing verifiers. The new technique has been implemented in the Crystal timing analyzer and experimental results comparing this method with those used in Crystal are included. Comparisons indicate that the ELogic-based approach, while slower than present approaches, provides a more robust and more accurate delay analysis at the switch level.