BOLT-a block oriented design specification language
DAC '81 Proceedings of the 18th Design Automation Conference
A MOS/LSI oriented logic simulator
DAC '81 Proceedings of the 18th Design Automation Conference
Design verification and performance analysis
DAC '78 Proceedings of the 15th Design Automation Conference
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
An accuration delay modeling technique for switch-level timing verification
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Path delay analysis for hierarchical building block layout system
DAC '83 Proceedings of the 20th Design Automation Conference
BOLT-a block oriented design specification language
DAC '81 Proceedings of the 18th Design Automation Conference
An automatic/interactive layout planning system for arbitrarily-sized rectangular building blocks
DAC '81 Proceedings of the 18th Design Automation Conference
Timing verification system based on delay time hierarchical nature
DAC '82 Proceedings of the 19th Design Automation Conference
Synchronous path analysis in MOS circuit simulator
DAC '82 Proceedings of the 19th Design Automation Conference
Hi-index | 0.00 |
The Path Analysis program provides logic and circuit design checking for signal propagation delay constraints. The program is useful for optimizing network performance. Checking and optimization are traditionally performed by manual inspection and incompletely verified by logic and circuit simulation. The Path Analysis program completely verifies signal propagation delays against design constraints. Checks are performed either with user supplied logic simulation data or parameters extracted from the physical IC layout information.