Computer-aided prediction of delays in LSI logic systems
DAC '73 Proceedings of the 10th Design Automation Workshop
Electrical considerations in the computer aided design of logic circuit interconnections
DAC '73 Proceedings of the 10th Design Automation Workshop
Design validation in hierarchical systems
DAC '75 Proceedings of the 12th Design Automation Conference
Design verification of large scientific computers
DAC '77 Proceedings of the 14th Design Automation Conference
Statistical failure analysis of system timing
IBM Journal of Research and Development
Verification of timing constraints on large digital systems
25 years of DAC Papers on Twenty-five years of electronic design automation
Timing verification and the timing analysis program
25 years of DAC Papers on Twenty-five years of electronic design automation
Path delay analysis for hierarchical building block layout system
DAC '83 Proceedings of the 20th Design Automation Conference
Hierarchical design verification for large digital systems
DAC '81 Proceedings of the 18th Design Automation Conference
A critical path delay check system
DAC '81 Proceedings of the 18th Design Automation Conference
A timing verification system based on extracted MOS/VLSI circuit parameters
DAC '81 Proceedings of the 18th Design Automation Conference
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
Speed and accuracy in digital network simulation based on structural modeling
DAC '82 Proceedings of the 19th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Developments in logic network path delay analysis
DAC '82 Proceedings of the 19th Design Automation Conference
Timing verification system based on delay time hierarchical nature
DAC '82 Proceedings of the 19th Design Automation Conference
Synchronous path analysis in MOS circuit simulator
DAC '82 Proceedings of the 19th Design Automation Conference
Timing analysis of computer hardware
IBM Journal of Research and Development
Static timing analysis for flexible TFT circuits
Proceedings of the 47th Design Automation Conference
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The successful development of high speed digital computer systems usually requires that maximum performance be obtained from the selected technology. An optimum system design can be pursued only with confidence that the necessary performance levels can be achieved by the system components.7,8 Without that confidence the alternative is a more pessimistic “worst case” system design. The necessary confidence can only be achieved by a continuing evaluation of the timing characteristics of the system components.