Hierarchical design verification for large digital systems
DAC '81 Proceedings of the 18th Design Automation Conference
A critical path delay check system
DAC '81 Proceedings of the 18th Design Automation Conference
A timing verification system based on extracted MOS/VLSI circuit parameters
DAC '81 Proceedings of the 18th Design Automation Conference
Design verification and performance analysis
DAC '78 Proceedings of the 15th Design Automation Conference
Computer-aided prediction of delays in LSI logic systems
DAC '73 Proceedings of the 10th Design Automation Workshop
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
TRIP: an automated technology mapping system
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A novel approach to accurate timing verification using RTL descriptions
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Integrated design system for supercomputer SX-1/SX-2
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
An effective delay analysis system for a large scale computer design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Path delay analysis for hierarchical building block layout system
DAC '83 Proceedings of the 20th Design Automation Conference
The CRITTER system: Automated critiquing of digital circuit designs
DAC '84 Proceedings of the 21st Design Automation Conference
A framework for hierarchical performance analysis
EURO-DAC '91 Proceedings of the conference on European design automation
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A hierarchical timing verification system is described. It can evaluate all logical paths in a chip without any specific manual input information, using a path tracing algorithm. This hierarchical approach can drastically reduce the number of logical paths to be traced and the corresponding computation time. This system is used for designing master slice (gate array) LSIs and building block LSIs.