Gprof: A call graph execution profiler
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Timing verification system based on delay time hierarchical nature
DAC '82 Proceedings of the 19th Design Automation Conference
| Hi-index | 0.00 |
The performance analysis of VLSI integrated circuits (ICs) with flat tools is slow and even sometimes impossible to complete. Some hierarchical tools have been developed to speed up the analysis of these large ICs. However, these hierarchical tools suffer from a poor interaction with the CAD database and poorly automatized operations. We introduce a general hierarchical framework for performance analysis to solve these problems. The circuit analysis is automatic under the proposed framework. Information that has been automatically abstracted in the hierarchy is kept in database properties along with the topological information. A limited software implementation of the framework, PREDICT, has also been developed to analyze the delay performance.