Statistical failure analysis of system timing
IBM Journal of Research and Development
Timing verification and the timing analysis program
25 years of DAC Papers on Twenty-five years of electronic design automation
Development of a timing analysis program for multiple clocked network
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Path delay analysis for hierarchical building block layout system
DAC '83 Proceedings of the 20th Design Automation Conference
Design verification and performance analysis
DAC '78 Proceedings of the 15th Design Automation Conference
A multiple delay simulator for MOS LSI circuits
DAC '80 Proceedings of the 17th Design Automation Conference
Speed and accuracy in digital network simulation based on structural modeling
DAC '82 Proceedings of the 19th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Timing verification system based on delay time hierarchical nature
DAC '82 Proceedings of the 19th Design Automation Conference
Developments in computer simulation of gate level physical logic
DAC '79 Proceedings of the 16th Design Automation Conference
Design verification system for large-scale LSI designs
IBM Journal of Research and Development
Timing analysis of computer hardware
IBM Journal of Research and Development
Static timing analysis for flexible TFT circuits
Proceedings of the 47th Design Automation Conference
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A computer program is described which was developed for LSI (large scale integrated) systems to resolve the uncertainties in transient delays prior to building the physical logic systems. This computer program represents a departure from the conventional logic simulation programs where unit delays are assumed for individual logic elements. The program takes into account all physical circuit variables at the mask composite stage in the design cycle. Transient delays are computed and inserted into the logic simulation program.