Path delay analysis for hierarchical building block layout system
DAC '83 Proceedings of the 20th Design Automation Conference
Computer-aided prediction of delays in LSI logic systems
DAC '73 Proceedings of the 10th Design Automation Workshop
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Developments in logic network path delay analysis
DAC '82 Proceedings of the 19th Design Automation Conference
Efficient algorithms for extracting the K most critical paths in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
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This paper describes the development of a timing analysis program for logic networks using both critical path and enumerative trace methods. The program utilizes the dynamic data structure of Pascal and its recursive computing power such that depth first search and breath first search can be carried out for delay calculations in a highly efficient manner. The program detects long and short paths between storage elements, setup and hold time violations of flip-flop, and minimum pulse width violations of clock signals.