Hierarchical design verification for large digital systems
DAC '81 Proceedings of the 18th Design Automation Conference
A critical path delay check system
DAC '81 Proceedings of the 18th Design Automation Conference
Design verification and performance analysis
DAC '78 Proceedings of the 15th Design Automation Conference
Race analysis of digital systems without logic simulation
DAC '71 Proceedings of the 8th Design Automation Workshop
Efficient algorithms for extracting the K most critical paths in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Timing analysis in a logic synthesis environment
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Timing- and constraint-oriented placement for interconnected LSIs in mainframe design
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A polynomial-time heuristic approach to approximate a solution to the false path problem
DAC '93 Proceedings of the 30th international Design Automation Conference
CADTOOLS: a CAD algorithm development system
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Development of a timing analysis program for multiple clocked network
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
An effective delay analysis system for a large scale computer design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Plug-in timing models for an abstract timing verifier
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Path delay analysis for hierarchical building block layout system
DAC '83 Proceedings of the 20th Design Automation Conference
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This paper discusses path delay analysis programs as an alternative to detailed logic simulation for finding timing problems in logic networks. Fundamentals of path delay analysis are reviewed, and several previously reported methods are surveyed. This is followed by a more detailed description of a delay analysis program that we have recently implemented. Our implementation uncovers a wide variety of timing problems and has a run time that is linearly proportional to the number of gates in the network. Other principle features are that timing information loss is minimized by treating 0-to-1 and 1-to-0 delays separately, and the user is given the capability of selectively disabling paths in order to discover timing problems that would otherwise remain hidden.