Accurate simulation of high speed computer logic
DAC '69 Proceedings of the 6th annual Design Automation Conference
Verification of timing constraints on large digital systems
25 years of DAC Papers on Twenty-five years of electronic design automation
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
Developments in logic network path delay analysis
DAC '82 Proceedings of the 19th Design Automation Conference
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Critical timing races (hazards) are a potential problem in digital systems consisting of a large number of interchangeable modules and replaceable integrated circuits. These hazards can be minimized by careful design procedures and reviews but will still exist due to system complexities. Systems have been proposed for simulating digital networks based on a time-sequenced logical tracing, but these systems require much host computer time and input stimuli to thoroughly exercise the system. The basis of the proposed race analysis system is that all critical races result in an improper flip-flop state. Each flip-flop input is traced, from logic element out-put to input, accumulating delays. Two basic algorithms are required and described to locate the racing of parallel paths on flip-flop inputs. This system requires minimal user inputs and can perform either a statistical or worst case race analysis.