ACM '65 Proceedings of the 1965 20th national conference
Non-integral event timing for digital logic simulation
DAC '76 Proceedings of the 13th Design Automation Conference
Fault simulation of digital logic utilizing a small host machine
DAC '72 Proceedings of the 9th Design Automation Workshop
Race analysis of digital systems without logic simulation
DAC '71 Proceedings of the 8th Design Automation Workshop
DAC '71 Proceedings of the 8th Design Automation Workshop
Speed and accuracy in digital network simulation based on structural modeling
DAC '82 Proceedings of the 19th Design Automation Conference
Developments in computer simulation of gate level physical logic
DAC '79 Proceedings of the 16th Design Automation Conference
A minicomputer-based logic circuit fault simulator
ACM SIGDA Newsletter
Using coverage to deploy formal verification in a simulation world
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
| Hi-index | 0.00 |
This paper presents a design verification logic simulation system which uses a ccurate timing information and propagation delay ambiguity in its circuit models. The case in favor of such a system is put forth. Methods for simulating propagation delay ambiguity and utilizing accurate circuit timing data are introduced. The time-sequenced simulation programming technique used in this system is described. Host computer memory and time requirement data from simulation test runs are reported.