Techniques for the simulation of computer logic
Communications of the ACM
Optimizing bit-time computer simulation
Communications of the ACM
SOSP '87 Proceedings of the eleventh ACM Symposium on Operating systems principles
Algorithms for accuracy enhancement in a hardware logic simulator
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Zero delay versus positive delay in an incremental switch-level simulator
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Hashed and hierarchical timing wheels: efficient data structures for implementing a timer facility
IEEE/ACM Transactions on Networking (TON)
Exclusive simulation of activity in digital networks
Communications of the ACM
On simulating networks of parallel processes in which simultaneous events may occur
Communications of the ACM
Modular requirements for digital logic simulation at a predefined functional level
ACM '72 Proceedings of the ACM annual conference - Volume 1
Tutorial: Compiling concurrent languages for sequential processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Vector coding techniques for high speed digital simulation
DAC '81 Proceedings of the 18th Design Automation Conference
Fault-test analysis techniques based on logic simulation
DAC '72 Proceedings of the 9th Design Automation Workshop
Accurate simulation of high speed computer logic
DAC '69 Proceedings of the 6th annual Design Automation Conference
A new algebraic procedure for the simulation of large digital networks
DAC '75 Proceedings of the 12th Design Automation Conference
DAC '75 Proceedings of the 12th Design Automation Conference
A new look at test generation and verification
DAC '77 Proceedings of the 14th Design Automation Conference
Serial/parallel event scheduling for the simulation of large systems
ACM '68 Proceedings of the 1968 23rd ACM national conference
Developments in computer simulation of gate level physical logic
DAC '79 Proceedings of the 16th Design Automation Conference
Modular requirements for digital logic simulation at a predefined functional level
ACM SIGDA Newsletter
Functional Partitioning and Simulation of Digital Circuits
IEEE Transactions on Computers
Fault insertion techniques and models for digital logic simulation
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
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MANY PUBLISHED efforts in the field of logical simulation indicate that the programming concept of “compiling and executing” is the most frequently used foundation for the construction of simulation programs. The technique to be described here represents a complete departure from the concept of “compiling and executing”. The basic framework for the simulation method to be presented is simply a close imitation of the structure and operation of a logical network. Applying this concept leads to a realistically operating “general purpose” simulator. The resulting simulation possibilities are—at least with respect to the field of logical simulation—relatively unexplored and unexploited. Simulation in other fields, e.g., the simulation of nerve nets by Reiss1, has preceded the field of logical simulation in taking advantage of the structure and operation of (neural) networks. The first success in applying these methods to the field of logical simulation has been reported by Case, et al2.