Fault insertion techniques and models for digital logic simulation

Authors:
Stephen A. Szygenda;Edward W. Thompson
Affiliations:
Southern Methodist University, Dallas, Texas;Southern Methodist University, Dallas, Texas
Venue:
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
Year:
1972

Citing 7
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Abstract

During the past few years it has become increasingly apparent that in order to design and develop highly reliable and maintainable digital logic systems it is necessary to be able to accurately simulate those systems. Not only is it necessary to be able to simulate a logic net as it was intended to behave, but it is also necessary to be able to model or simulate the behavior of the logic net when it contains a physical defect. (The representation of a physical defect is known as a fault.) The behavioral simulation of a digital logic net which contains a physical defect, or fault, is known as digital fault simulation.