Application of Ternary Algebra to the Study of Static Hazards
Journal of the ACM (JACM)
High-speed fault simulation for UNIVAC 1107 computer system
ACM '68 Proceedings of the 1968 23rd ACM national conference
Computer-Aided Design: Simulation of Digital Design Logic
IEEE Transactions on Computers
A model and implementation of a universal time delay simulator for large digital nets
AFIPS '70 (Spring) Proceedings of the May 5-7, 1970, spring joint computer conference
On the Three-Valued Simulation of Digital Systems
IEEE Transactions on Computers
Modeling and Digital Simulation for Design Verification and Diagnosis
IEEE Transactions on Computers
Fault insertion techniques and models for digital logic simulation
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
Asynchronous Logic Circuits and Sheaf Obstructions
Electronic Notes in Theoretical Computer Science (ENTCS)
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Digital logic simulation is the process whereby the action of a logic circuit due to a specified input is predicted based upon some model of the circuit. Logic simulation is becoming increasingly necessary as larger and more complex computers are built. Because of the cost of building hardware it is not wise to commit a circuit design to manufacture without first verifying the operation of the circuit by simulation. This is true even for large computers (say 50,000 gates) where simulation will eliminate many logic errors and may save construction of a prototype model. Simulation may be used to predict the output of the circuit due to specified faults as well as to predict the output of the good (fault free) circuit. A dictionary is generally compiled of the output of the circuit in the presence of known faults. By comparing the actual (perhaps faulty) circuit output to the correct output, it is possible to detect and diagnose a fault in the circuit.