Application of Ternary Algebra to the Study of Static Hazards
Journal of the ACM (JACM)
Functional simulation in the lamp system
DAC '76 Proceedings of the 13th Design Automation Conference
High-speed fault simulation for UNIVAC 1107 computer system
ACM '68 Proceedings of the 1968 23rd ACM national conference
Timing analysis for digital fault simulation using assignable delays
DAC '74 Proceedings of the 11th Design Automation Workshop
Computer-Aided Design: Simulation of Digital Design Logic
IEEE Transactions on Computers
A Deductive Method for Simulating Faults in Logic Circuits
IEEE Transactions on Computers
Comparison of Parallel and Deductive Fault Simulation Methods
IEEE Transactions on Computers
A model and implementation of a universal time delay simulator for large digital nets
AFIPS '70 (Spring) Proceedings of the May 5-7, 1970, spring joint computer conference
Simulation of large asynchronous logic circuits using an ambiguous gate model
AFIPS '71 (Fall) Proceedings of the November 16-18, 1971, fall joint computer conference
Fault insertion techniques and models for digital logic simulation
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
A three-value computer design verification system
IBM Systems Journal
Hazard detection in combinational and sequential switching circuits
IBM Journal of Research and Development
Design for Testability A Survey
IEEE Transactions on Computers
IEEE Transactions on Computers
Fault tolerance by means of external monitoring of computer systems
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
Correlating testability with fault detection
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
LSI logic testing: an overview
IEEE Transactions on Computers
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There are many activities included under the category of design automation for integrated circuits. Some of these activities include packaging, placement, routing, interactive graphics, device data bases, and digital simulation; for the purpose of logic verification, timing analysis, and diagnostic test verification. One might also include high-level simulation, such as register transfer simulation, for the purpose of initial logic verification. This paper will be oriented towards modeling and implementation questions which arise when one is attempting to implement an extremely accurate digital simulator for the purposes of logic and design verification and fault simulation. Simulators for these purposes are now extremely important and occupy a major role in any design automation system. These systems are also very expensive and therefore the incorrect answers to a variety of questions which arise during the process of developing such simulators can be disastrous. This paper shall attempt to acquaint the reader with questions that have arisen over the years in terms of developing these simulators and what some of the possible answers are, and their respective tradeoffs. Although the successes, and, equally the failures, of many people have contributed to the present state of the art of digital simulators, one particular simulator, the one the authors are most intimately involved with, will be used as a source of detailed examples demonstrating many of the questions to be discussed.