Comparison of Parallel and Deductive Fault Simulation Methods

Authors:
H. Y. -P. Chang;S. G. Chappell;C. H. Elmendorf;L. D. Schmidt
Affiliations:
Bell Laboratories;-;-;-
Venue:
IEEE Transactions on Computers
Year:
1974

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Abstract

A comparison of the central processing unit (CPU) time and storage requirements for the parallel and deductive fault simulation techniques is presented. Versions of a parallel and deductive simulator were implemented and the comparison performed on an IBM System/360 Model 67 by simulating representative circuits including shift registers, sequencers, counters, two memory units, and a processor. Th