LCC simulators speed development of synchronous hardware
Computer Design
SSIM: a software levelized compiled-code simulator
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
COSMOS: a compiled simulator for MOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Scheduling high-level blocks for functional simulation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Hardware logic simulation by compilation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Comparison of Parallel and Deductive Fault Simulation Methods
IEEE Transactions on Computers
Automatic generation of compiled simulations through program specialization
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An evaluation of the Chandy-Misra-Bryant algorithm for digital logic simulation
ACM Transactions on Modeling and Computer Simulation (TOMACS) - Special issue on parallel and distributed systems performance
Two new techniques for compiled multi-delay logic simulation
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Unit delay simulation with the inversion algorithm
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Parallel multi-delay simulation
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A case against event-driven simulation for digital system design
ANSS '91 Proceedings of the 24th annual symposium on Simulation
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The PC-set method and the parallel technique are two methods for performing compiled unit-delay simulation. The PC-set method analyzes the network, determines the set of potential change times for each net, and generates gate simulations for each potential change. The parallel technique, which is based on the concept of parallel fault simulation, is faster and generates less code than the PC-method, but is less flexible. Benchmark comparisons with interpreted event-driven simulation show a factor of four improvement for the PC-set method and a factor of ten improvement for the parallel technique.