SLS—a fast switch level simulator for verification and fault coverage analysis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Fast Algorithms for Solving Path Problems
Journal of the ACM (JACM)
Massively parallel switch-level simulation: a feasibility study
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Automatic generation of behavioral models from switch-level descriptions
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Test pattern generation for sequential MOS circuits by symbolic fault simulation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Logic simulation on massively parallel architectures
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Parallelizing a new class of large applications over high-speed networks
PPOPP '91 Proceedings of the third ACM SIGPLAN symposium on Principles and practice of parallel programming
A portable platform for distributed event environments
PADD '91 Proceedings of the 1991 ACM/ONR workshop on Parallel and distributed debugging
Techniques for unit-delay compiled simulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
LECSIM: a levelized event driven compiled logic simulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Network-based multicomputers: an emerging parallel architecture
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Algorithms for fast, memory efficient switch-level fault simulation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Automatic generation of compiled simulations through program specialization
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Mapping switch-level simulation onto gate-level hardware accelerators
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
OEsim: a simulator for timing behavior
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Symbolic simulation—techniques and applications
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Two new techniques for compiled multi-delay logic simulation
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
EURO-DAC '92 Proceedings of the conference on European design automation
Evaluation of parts by mixed-level DC-connected components in logic simulation
DAC '93 Proceedings of the 30th international Design Automation Conference
Linking BDD-based symbolic evaluation to interactive theorem-proving
DAC '93 Proceedings of the 30th international Design Automation Conference
Design management using dynamically defined flows
DAC '93 Proceedings of the 30th international Design Automation Conference
A framework for dynamic program analyzers
OOPSLA '93 Proceedings of the eighth annual conference on Object-oriented programming systems, languages, and applications
Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
VHDL switch level fault simulation
EURO-DAC '94 Proceedings of the conference on European design automation
Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Logic verification methodology for PowerPC microprocessors
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Analysis of switch-level faults by symbolic simulation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A multiple-dominance switch-level model for simulation of short faults
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
The Unison algorithm: fast evaluation of Boolean expressions
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Verification of electronic systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Oscillation control in logic simulation using dynamic dominance graphs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
The automatic generation of functional test vectors for Rambus designs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Network-Based Multicomputers: A Practical Supercomputer Architecture
IEEE Transactions on Parallel and Distributed Systems
Parallel multi-delay simulation
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A Variational Approach to Recovering Depth From Defocused Images
IEEE Transactions on Pattern Analysis and Machine Intelligence
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Fast incremental circuit analysis using extracted hierarchy
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Advances in functional abstraction from structure
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A case against event-driven simulation for digital system design
ANSS '91 Proceedings of the 24th annual symposium on Simulation
Digital MOS circuit partitioning with symbolic modeling
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A switch level fault simulation environment
Proceedings of the 37th Annual Design Automation Conference
Efficient state representation for symbolic simulation
Proceedings of the 39th annual Design Automation Conference
Incremental Switch-Level Analysis
IEEE Design & Test
Test Generation for Current Testing (CMOS ICs)
IEEE Design & Test
A Value System for Switch-Level Modeling
IEEE Design & Test
Dynamic Functional Testing for VLSI Circuits
IEEE Design & Test
Formal Verification Using Edge-Valued Binary Decision Diagrams
IEEE Transactions on Computers
Verisym: Verifying Circuits by Symbolic Simulation
Formal Methods in System Design
Formal Verification Methods for Industrial Hardware Design
SOFSEM '01 Proceedings of the 28th Conference on Current Trends in Theory and Practice of Informatics Piestany: Theory and Practice of Informatics
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Verifying real-time properties of MOS-transistor circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A symbolic core approach to the formal verification of integrated mixed-mode applications
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Is Compiled Simulation Really Faster than Interpreted Simulation?
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Switch-level modeling of feedback faults using global oscillation control
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
NETHDL: abstraction of schematics to high-level HDL
EURO-DAC '90 Proceedings of the conference on European design automation
Derivation of signal flow for switch-level simulation
EURO-DAC '90 Proceedings of the conference on European design automation
Parallel switch-level simulation for VLSI
EURO-DAC '91 Proceedings of the conference on European design automation
Using conjugate symmetries to enhance gate-level simulations
Proceedings of the conference on Design, automation and test in Europe: Proceedings
The design of an asynchronous microprocessor
ACM SIGARCH Computer Architecture News
Proceedings of the 44th annual Design Automation Conference
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
Event-driven gate-level simulation with GP-GPUs
Proceedings of the 46th Annual Design Automation Conference
GCS: high-performance gate-level simulation with GP-GPUs
Proceedings of the Conference on Design, Automation and Test in Europe
Gate-Level Simulation with GPU Computing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The simulation automation system (SAS); concepts, implementation, and results
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A symbolic modelling approach for the formal verification of integrated mixed-mode systems
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
Proceedings of the 33rd ACM SIGPLAN conference on Programming Language Design and Implementation
On the use of GP-GPUs for accelerating compute-intensive EDA applications
Proceedings of the Conference on Design, Automation and Test in Europe
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The COSMOS simulator provides fast and accurate switch-level modeling of MOS digital circuits. It attains high performance by preprocessing the transistor network into a functionally equivalent Boolean representation. This description, produced by the symbolic analyzer ANAMOS, captures all aspects of switch-level networks including bidirectional transistors, stored charge, different signal strengths, and indeterminate (X) logic values. The LGCC program translates the Boolean representation into a set of machine language evaluation procedures and initialized data structures. These procedures and data structures are compiled along with code implementing the simulation kernel and user interface to produce the simulation program. The simulation program runs an order of magnitude faster than our previous simulator MOSSIM II.