COSMOS: a compiled simulator for MOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Hierarchical circuit verification
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Efficient netlist comparison using hierarchy and randomization
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
SLS—a fast switch level simulator for verification and fault coverage analysis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
DAC '83 Proceedings of the 20th Design Automation Conference
Circuit recognition and verification based on layout information
DAC '81 Proceedings of the 18th Design Automation Conference
Digital MOS circuit partitioning with symbolic modeling
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Hybrid compiled/interpreted simulation of MOS circuits
EURO-DAC '91 Proceedings of the conference on European design automation
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We present an algorithm for extracting a two-level subnetwork hierarchy from flat netlists and its application to incremental circuit analysis in the COSMOS compiled switch-level simulator. Incremental operation is achieved by using the file system as a large hash table that retains information over many executions of the incremental analyzer. The hierarchy extraction algorithm computes a hash signature for each subnetwork by coloring vertices in a manner similar to wirelist-comparison programs, then identifies duplicates using standard hash-table techniques. Its application decreases the network preprocessing time for COSMOS by nearly an order of magnitude.