The C programming language
Introduction to VLSI Systems
A hardware assisted design rule check architecture
DAC '82 Proceedings of the 19th Design Automation Conference
KAHLUA: a hierarchical circuit disassembler
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
The role of timing verification in layout synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Time efficient VLSI artwork analysis algorithms in GOALIE2
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Fast incremental circuit analysis using extracted hierarchy
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
ETS-A: A New Electrothermal Simulator for CMOS VLSI Circuits
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Hierarchical layout verification
DAC '84 Proceedings of the 21st Design Automation Conference
Hierarchical layout verification for submicron designs
EURO-DAC '90 Proceedings of the conference on European design automation
Technology migration technique for designs with strong RET-driven layout restrictions
Proceedings of the 2005 international symposium on Physical design
Technology migration techniques for simplified layouts with restrictive design rules
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Incremental analysis of large VLSI Layouts
Integration, the VLSI Journal
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This paper describes the design, implementation and performance of a fiat edge-based circuit extractor for NMOS circuits. The extractor is able to work on large and complex designs, it can handle arbitrary geometry, and outputs a comprehensive wirelist. Measurements show that the run time of the edge-based algorithm used is linear in size of the circuit, with low implementation overheads. The extractor is capable of analyzing a circuit with 20,000 transistors in less than 30 minutes of CPU time on a VAX 11/780. The high performance of the extractor has changed the role that a circuit extractor played in the design process, as it is now possible to extract a chip a number of times during the same session.