Hierarchical circuit extraction with detailed parasitic capacitance
DAC '83 Proceedings of the 20th Design Automation Conference
Symbolic Parasitic Extractor for Circuit Simulation (SPECS)
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '84 Proceedings of the 21st Design Automation Conference
Hierarchical layout verification
DAC '84 Proceedings of the 21st Design Automation Conference
Switch-level delay models for digital MOS VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
EXCL: A circuit extractor for IC designs
DAC '84 Proceedings of the 21st Design Automation Conference
DAC '81 Proceedings of the 18th Design Automation Conference
Architecture of SOAR: Smalltalk on a RISC
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
HPEX: a hierarchical parasitic circuit extractor
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
RED: resistance extraction for digital simulation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
REX—a VLSI parasitic extraction tool for electromigration and signal analysis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Using articulation nodes to improve the efficiency of finite-element based resistance extraction
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Analyzing CMOS power supply networks using Ariel
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Fast incremental circuit analysis using extracted hierarchy
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Technology independent arbitrary device extractor
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Efficient algorithms for polygon to trapezoid decomposition and trapezoid corner stitching
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Hierarchical layout verification for submicron designs
EURO-DAC '90 Proceedings of the conference on European design automation
IPRAIL: intellectual property reuse-based analog IC layout automation
Integration, the VLSI Journal - Special issue on analog and mixed-signal IC design and design methodologies
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Hierarchical extraction and verification of symmetry constraints for analog layout automation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
An efficient algorithm for partitioning parameterized polygons into rectangles
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Partitioning parameterized 45-degree polygons with constraint programming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Incremental analysis of large VLSI Layouts
Integration, the VLSI Journal
A parallel dual-scanline algorithm for partitioning parameterized 45-degree polygons
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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We have implemented a fast hierarchical circuit extractor for the Magic VLSI layout system. The keys to its speed are a new algorithm based on corner-stitching, and its ability to extract cells incrementally. Because the extractor is incremental, typically only a few cells must be re-extracted when the layout changes. The extractor computes circuit connectivity and transistor dimensions, both internodal and substrate parasitic capacitance, and parasitic resistances. It is parameterized to work across a wide range of MOS technologies.