DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A technology independent approach to hierarchical IC layout extraction
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Multidimensional binary search trees used for associative searching
Communications of the ACM
Hierarchical circuit extraction with detailed parasitic capacitance
DAC '83 Proceedings of the 20th Design Automation Conference
Hierarchical electromigration reliability diagnosis for VLSI interconnects
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Analyzing CMOS power supply networks using Ariel
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
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A hierarchical parasitic circuit extractor HPEX for Manhattan layouts is described. HPEX can model interconnection lines as distributed lumped circuits directly from a circuit layout by using analytical formulas instead of numerical methods. The difference in feature sizes between mask layouts and actual fabricated conductors is also taken into account by a geometrical preprocessing algorithm based on a novel Y-X scanline method and a simple rectangle data structure. In addition, a simple and accurate node reduction technique based on the concept of Elmore's delay is employed in HPEX to make layout verification simpler. All features mentioned above clearly indicate that HPEX will be a promising tool in verifying VLSI system performance especially when interconnect parasitics associated with VLSI circuits are taken into consideration.