Circuit recognition and verification based on layout information
DAC '81 Proceedings of the 18th Design Automation Conference
ARTWORK ANALYSIS TOOL FOR VLSI CIRCUITS
ARTWORK ANALYSIS TOOL FOR VLSI CIRCUITS
KAHLUA: a hierarchical circuit disassembler
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
HPEX: a hierarchical parasitic circuit extractor
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
The role of timing verification in layout synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
RISCE—a reduced instruction set circuit extractor for hierarchical VLSI layout verification
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Integrated VLSI CAD systems at Digital Equipment Corporation
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Hierarchical circuit verification
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Hierarchical layout verification
DAC '84 Proceedings of the 21st Design Automation Conference
Hierarchical layout verification for submicron designs
EURO-DAC '90 Proceedings of the conference on European design automation
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This paper describes a hierarchical MOS layout verification program called IV. IV extracts a circuit netlist from a MOS layout and then compares this netlist to a reference circuit netlist obtained from a schematic. The circuit extraction phase of IV is described in detail. A unique characteristic of the program is the treatment of parasitic capacitance. IV is currently being used in a production environment to extract circuits in a variety of NMOS and CMOS processes.