Introduction to VLSI Systems
Hierarchical circuit extraction with detailed parasitic capacitance
DAC '83 Proceedings of the 20th Design Automation Conference
Hierarchical layout verification
DAC '84 Proceedings of the 21st Design Automation Conference
Circuit recognition and verification based on layout information
DAC '81 Proceedings of the 18th Design Automation Conference
A hierarchical approach for layout versus circuit consistency check
DAC '80 Proceedings of the 17th Design Automation Conference
Programs for verifying circuit connectivity of mos/lsi mask artwork
DAC '82 Proceedings of the 19th Design Automation Conference
Understanding hierarchical design
Understanding hierarchical design
RISCE—a reduced instruction set circuit extractor for hierarchical VLSI layout verification
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Fast incremental circuit analysis using extracted hierarchy
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Incremental Switch-Level Analysis
IEEE Design & Test
Hierarchical layout verification for submicron designs
EURO-DAC '90 Proceedings of the conference on European design automation
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One of the crucial steps in designing VLSI circuits is to verify the correctness of the layout of the circuitry. Traditionally, this verification step is done by first flattering out the circuit hierarchy. This approach requires a substantial amount of computational overhead even for circuits that are relatively small. In this paper, a connectivity verification algorithm which exploits circuit hierarchy is presented. This algorithm works most efficiently with big circuits and is therefore useful for verifying VLSI circuits.