Circuit recognition and verification based on layout information
DAC '81 Proceedings of the 18th Design Automation Conference
Automatic VLSI layout verification
DAC '81 Proceedings of the 18th Design Automation Conference
MOSSIM: A switch-level simulator for MOS LSI
DAC '81 Proceedings of the 18th Design Automation Conference
A hierarchical approach for layout versus circuit consistency check
DAC '80 Proceedings of the 17th Design Automation Conference
An integrated mask artwork analysis system
DAC '80 Proceedings of the 17th Design Automation Conference
Design rule checking and analysis of IC mask designs
DAC '76 Proceedings of the 13th Design Automation Conference
Fast algorithms for LSI artwork analysis
DAC '77 Proceedings of the 14th Design Automation Conference
A layout checking system for large scale integrated circuits
DAC '77 Proceedings of the 14th Design Automation Conference
Topological analysis for VLSI circuits
DAC '79 Proceedings of the 16th Design Automation Conference
Comparing structurally different views of a VLSI design
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A circuit comparison system with rule-based functional isomorphism checking
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A circuit comparison system for bipolar linear LSI
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Hierarchical circuit verification
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
Consistency checking for MOS/VLSI circuits
DAC '83 Proceedings of the 20th Design Automation Conference
Hierarchical layout verification
DAC '84 Proceedings of the 21st Design Automation Conference
MGX: An integrated symbolic layout system for VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
Evaluating responses containing both correct and incorrect information
MATH'08 Proceedings of the 13th WSEAS international conference on Applied mathematics
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This paper describes three programs which perform connectivity rule check, logic gate recognition for logic simulation and circuit connectivity comparison. These programs have been developed for verifying circuit connectivity extracted from mask artwork. Powerful algorithms are used in these programs, including a heuristic graph comparison algorithm, to realize highly practical verification aids. Through the combined use of these programs, more cost-effective verification is possible.