Design rule checking and analysis of IC mask designs
DAC '76 Proceedings of the 13th Design Automation Conference
Automatic circuit analysis based on mask information
DAC '76 Proceedings of the 13th Design Automation Conference
The automatic recognition of silicon gate transistor geometries: An LSI design aid program
DAC '76 Proceedings of the 13th Design Automation Conference
An artwork design verification system
DAC '75 Proceedings of the 12th Design Automation Conference
CRITIC - an integrated circuit design rule checking program
DAC '74 Proceedings of the 11th Design Automation Workshop
MAP: A user-controlled automated Mask Analysis Program
DAC '74 Proceedings of the 11th Design Automation Workshop
Generating incremental VLSI compaction spacing constraints
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
KAHLUA: a hierarchical circuit disassembler
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
SLIM - The translation of symbolic layouts into mask data
25 years of DAC Papers on Twenty-five years of electronic design automation
An O (N log N) algorithm for boolean mask operations
25 years of DAC Papers on Twenty-five years of electronic design automation
Hierarchical analysis of IC artwork with user defined abstraction rules
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
An O (N log N) algorithm for Boolean mask operations
DAC '81 Proceedings of the 18th Design Automation Conference
A concurrent pattern operation algorithm for VLSI mask data
DAC '81 Proceedings of the 18th Design Automation Conference
Efficient Boolean operations on IC masks
DAC '81 Proceedings of the 18th Design Automation Conference
Circuit recognition and verification based on layout information
DAC '81 Proceedings of the 18th Design Automation Conference
Automatic VLSI layout verification
DAC '81 Proceedings of the 18th Design Automation Conference
A color graphics system for I.C. mask design and analysis
DAC '78 Proceedings of the 15th Design Automation Conference
Design rule verification based on one dimensional scans
DAC '78 Proceedings of the 15th Design Automation Conference
The evolution of design automation to meet the challanges of VLSI
DAC '80 Proceedings of the 17th Design Automation Conference
Developments in verification of design correctness (A Tutorial)
DAC '80 Proceedings of the 17th Design Automation Conference
Design integrity and immunity checking: A new look at layout verification and design rule checking
DAC '80 Proceedings of the 17th Design Automation Conference
An integrated mask artwork analysis system
DAC '80 Proceedings of the 17th Design Automation Conference
A hierarchical bit-map format for the representation of IC mask data
DAC '80 Proceedings of the 17th Design Automation Conference
SLIM-the translation of symbolic layouts into mask data
DAC '80 Proceedings of the 17th Design Automation Conference
A hardware assisted design rule check architecture
DAC '82 Proceedings of the 19th Design Automation Conference
Programs for verifying circuit connectivity of mos/lsi mask artwork
DAC '82 Proceedings of the 19th Design Automation Conference
A “non-restrictive” artwork verification program for printed circuit boards
DAC '82 Proceedings of the 19th Design Automation Conference
VLSI tools and architectures: Putting the new technology to work
CSC-83 Proceedings of the 1983 computer science conference
Unified Shapes Checker - a checking tool for LSI
DAC '79 Proceedings of the 16th Design Automation Conference
LSI layout checking using bipolar device recognition technique
DAC '79 Proceedings of the 16th Design Automation Conference
The design of an efficient data base to support an interactive LSI layout system
DAC '79 Proceedings of the 16th Design Automation Conference
Topological analysis for VLSI circuits
DAC '79 Proceedings of the 16th Design Automation Conference
Circuit recognition and verification from bipolar and MOS layout information
ACM SIGDA Newsletter
| Hi-index | 0.00 |
Representative algorithms for IC mask artwork analysis are described and compared. A novel IC mask analysis algorithm is described which does not restrict the representation of artwork, permits a wide range of functions, avoids pathologies, and achieves good runtime and tolerable main memory demands, even for LSI applications. Under reasonable assumptions about the distribution of artwork within the chip area, the algorithm is shown to achieve an expected runtime complexity of 0(E**(3/2)), where E is the number of edges in the artwork. Experience with LSI circuits is described.