The art of computer programming, volume 3: (2nd ed.) sorting and searching
The art of computer programming, volume 3: (2nd ed.) sorting and searching
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
A hierarchical bit-map format for the representation of IC mask data
DAC '80 Proceedings of the 17th Design Automation Conference
Design rule checking and analysis of IC mask designs
DAC '76 Proceedings of the 13th Design Automation Conference
The automatic recognition of silicon gate transistor geometries: An LSI design aid program
DAC '76 Proceedings of the 13th Design Automation Conference
Fast algorithms for LSI artwork analysis
DAC '77 Proceedings of the 14th Design Automation Conference
LSI layout checking using bipolar device recognition technique
DAC '79 Proceedings of the 16th Design Automation Conference
Topological analysis for VLSI circuits
DAC '79 Proceedings of the 16th Design Automation Conference
Linear lists and priority queues as balanced binary trees
Linear lists and priority queues as balanced binary trees
KAHLUA: a hierarchical circuit disassembler
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Circuit extraction on a message-based multiprocessor
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Mixed-signal switching noise analysis using Voronoi-tessellated substrate macromodels
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Layout extraction and verification methodology CMOS I/O circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Mask verification on the connection machine
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Time efficient VLSI artwork analysis algorithms in GOALIE2
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Symbolic hierarchical artwork generation system
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A time and space efficient net extractor
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Efficient algorithms for polygon to trapezoid decomposition and trapezoid corner stitching
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Interconnect parasitic extraction in the digital IC design methodology
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Test Generation for Current Testing (CMOS ICs)
IEEE Design & Test
Fast Computation of Substrate Resistances in Large Circuits
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Critical area extraction of extra material soft faults
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Hierarchical critical area extraction with the EYE tool
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
HEX: An instruction-driven approach to feature extraction
DAC '83 Proceedings of the 20th Design Automation Conference
Space efficient algorithms for VLSI artwork analysis
DAC '83 Proceedings of the 20th Design Automation Conference
The scan line approach to design rules checking: Computational experiences
DAC '84 Proceedings of the 21st Design Automation Conference
A mixed-mode extraction flow for high performance microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Efficient fracturing of all angle shaped VLSI mask pattern data
Integration, the VLSI Journal
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A new algorithm is presented which calculates Boolean combinations (AND, OR, EXOR, AND NOT) between two layers of an integrated circuit layout. Input and output of the algorithm is an edgebased description of the set of polygons which represent the artwork. The algorithm has O (N log N) time and O (@@@@N) space complexity, i.e. it is faster than previously published methods. Moreover, we believe that it is easier to understand and to implement than the previously leading method in the field.