Layout extraction and verification methodology CMOS I/O circuits

Authors:
Tong Li;Sung-Mo Kang
Affiliations:
Dept. of Computer Science, Coordinated Science Laboratory, Univ. of Illinois at Urbana-Champaign;Dept. of Electrical and Computer Engineering, Coordinated Science Laboratory, Univ. of Illinois at Urbana-Champaign
Venue:
DAC '98 Proceedings of the 35th annual Design Automation Conference
Year:
1998

Citing 2
Cited 2

A layout verification system for analog bipolar integrated circuits

DAC '83 Proceedings of the 20th Design Automation Conference
An O (N log N) algorithm for Boolean mask operations

DAC '81 Proceedings of the 18th Design Automation Conference

Substrate modeling and lumped substrate resistance extraction for CMOS ESD/latchup circuit simulation

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
VeriCDF: a new verification methodology for charged device failures

Proceedings of the 39th annual Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a layout extraction and verification methodology which targets reliability-driven I/O design for CMOS VLSI chip, specifically to guard against electrostatic discharge (ESD) stress and latchup. We propose a new device extraction approach to identify devices commonly used in CMOS I/O circuits including MOS transistors, field transistors, diffusion and well resistors, diodes and silicon controlled rectifiers (SCRs), etc. Unlike other extractors, our extractor identifies circuit-level netlist based on the specified ESD stress condition. In addition, novel techniques are proposed for the identification of parasitic bipolar junction transistors (BJTs).