The C programming language
Plane-sweep algorithms for intersecting geometric figures
Communications of the ACM
Introduction to VLSI Systems
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
An O (N log N) algorithm for Boolean mask operations
DAC '81 Proceedings of the 18th Design Automation Conference
Efficient Boolean operations on IC masks
DAC '81 Proceedings of the 18th Design Automation Conference
An integrated mask artwork analysis system
DAC '80 Proceedings of the 17th Design Automation Conference
A hierarchical bit-map format for the representation of IC mask data
DAC '80 Proceedings of the 17th Design Automation Conference
Automatic circuit analysis based on mask information
DAC '76 Proceedings of the 13th Design Automation Conference
The automatic recognition of silicon gate transistor geometries: An LSI design aid program
DAC '76 Proceedings of the 13th Design Automation Conference
A hardware assisted design rule check architecture
DAC '82 Proceedings of the 19th Design Automation Conference
Topological analysis for VLSI circuits
DAC '79 Proceedings of the 16th Design Automation Conference
Mask verification on the connection machine
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
RISCE—a reduced instruction set circuit extractor for hierarchical VLSI layout verification
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Time efficient VLSI artwork analysis algorithms in GOALIE2
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A subjective review of compaction (tutorial session)
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Effective use of virtual grid compaction in macro-module generators
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A time and space efficient net extractor
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
CSC '85 Proceedings of the 1985 ACM thirteenth annual conference on Computer Science
Post-Layout Verification of the WE DSP32 Digital Signal Processor
IEEE Design & Test
An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
ACM Transactions on Database Systems (TODS)
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We present algorithms for performing connectivity analysis, transistor identification, and boolean geometric operations with region numbering. Previous methods all require O(n) space where n is the number of edges in the circuit artwork; our method takes only O(@@@@n) space and can therefore handle circuits of any foreseeable size. Our algorithms are based on traditional scanline techniques in such a way that any implementation of our method will be at least as fast, as well as more compact. Statistics on one such implementation are presented.