A time and space efficient net extractor

Authors:
Surendra Nahar;Sartaj Sahni
Affiliations:
University of Minnesota;University of Minnesota
Venue:
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Year:
1986

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Incremental analysis of large VLSI Layouts

Integration, the VLSI Journal

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Abstract

We develop an efficient algorithm for net extraction. This algorithm is able to efficiently handle very large layouts even when memory is limited. This is done by effectively using disk storage. The algorithm has been programmed in Fortran and is superior to other existing net extractors.