An artwork design verification system

  • Authors:
  • H. S. Baird;Y. E. Cho

  • Affiliations:
  • -;-

  • Venue:
  • DAC '75 Proceedings of the 12th Design Automation Conference
  • Year:
  • 1975

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Abstract

Manual and semi-automatic methods of Integrated circuit layout are prone to errors which are often detected only after a sample chip has been fabricated. This paper describes two design verification programs that detect and identify such errors earlier in the design cycle through comparing a designer's logic description with the finished mask artwork. These programs are part of an integrated CAD system developed at RCA laboratories.