FLOSS: an approach to automated layout for high-volume designs
25 years of DAC Papers on Twenty-five years of electronic design automation
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Graph-optimization techniques for IC layout and compaction
DAC '83 Proceedings of the 20th Design Automation Conference
Improved compaction by minimized length of wires
DAC '83 Proceedings of the 20th Design Automation Conference
Space efficient algorithms for VLSI artwork analysis
DAC '83 Proceedings of the 20th Design Automation Conference
A symbolic-interconnect router for custom IC design
DAC '84 Proceedings of the 21st Design Automation Conference
A hiererachical, error-tolerant compactor
DAC '84 Proceedings of the 21st Design Automation Conference
Interactive compaction router for VLSI layout
DAC '84 Proceedings of the 21st Design Automation Conference
Plowing: Interactive stretching and compaction in magic
DAC '84 Proceedings of the 21st Design Automation Conference
Amoeba: A symbolic VLSI layout system
DAC '84 Proceedings of the 21st Design Automation Conference
DAC '81 Proceedings of the 18th Design Automation Conference
SLIM-the translation of symbolic layouts into mask data
DAC '80 Proceedings of the 17th Design Automation Conference
IC mask layout with a single conductor layer
DAC '70 Proceedings of the 7th Design Automation Workshop
An artwork design verification system
DAC '75 Proceedings of the 12th Design Automation Conference
Computational Aspects of VLSI
Nutcracker: an efficient and intelligent channel spacer
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
An efficient two-dimensional layout compaction algorithm
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Plowing: modifying cells and routing 45:9D - layouts
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A new hierarchical layout compactor using simplified graph models
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Optimal graph constraint reduction for symbolic layout compaction
DAC '93 Proceedings of the 30th international Design Automation Conference
Symbolic layout compaction review
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Compaction with incremental over-constraint resolution
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
An efficient compactor for 45° layout
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Connectivity biased channel construction and ordering for building-block layout
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Two-dimensional compaction by “zone refining”
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Minplex—a compactor that minimizes the bounding rectangle and individual rectangles in a layout
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Automatic process migration of datapath hard IP libraries
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Two-Dimensional Layout Migration by Soft Constraint Satisfaction
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Chameleon ART: a non-optimization based analog design migration framework
Proceedings of the 43rd annual Design Automation Conference
A new control strategy for an artificial intelligence approach to VLSI layout compaction
Integration, the VLSI Journal
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Compaction is the CAD tool used to pack rough sketches or symbolic diagrams to produce IC layouts. Manual compaction is tedious, time-consuming, and error-prone; automated compaction tools can greatly shorten the layout design cycle. This paper reviews the historical background and the major developments in the field of compaction, emphasizing subjective evaluations rather than objective descriptions. The major approaches covered are constraint-graph, shear-line, and virtual-grid. Various ideas for further reducing chip area (such as inserting jog points, shortening wires, dense packing, 2-D compaction, and interactive tools) are also discussed. Because of the critical role of efficient algorithms in VLSI CAD systems, analyses of computational complexities are also included.