Graph-optimization techniques for IC layout and compaction
DAC '83 Proceedings of the 20th Design Automation Conference
Improved compaction by minimized length of wires
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
Understanding hierarchical design
Understanding hierarchical design
Generating incremental VLSI compaction spacing constraints
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A hierarchy preserving hierarchical compactor
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Datapath generator based on gate-level symbolic layout
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A framework for industrial layout generators
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
VLSI layout compaction using radix priority search trees
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A new hierarchical layout compactor using simplified graph models
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Optimal graph constraint reduction for symbolic layout compaction
DAC '93 Proceedings of the 30th international Design Automation Conference
Symbolic layout compaction review
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Compaction with incremental over-constraint resolution
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
HIMALAYAS — a hierarchical compaction system with a minimized constraint set
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A subjective review of compaction (tutorial session)
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Symbolic hierarchical artwork generation system
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Efficient algorithms for debugging timing constraint violations
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Proceedings of the tenth international symposium on Hardware/software codesign
A symbolic-interconnect router for custom IC design
DAC '84 Proceedings of the 21st Design Automation Conference
VTIcompose - a powerful graphical chip assembly tool
DAC '84 Proceedings of the 21st Design Automation Conference
Automatic process migration of datapath hard IP libraries
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Provably efficient algorithms for resolving temporal and spatial difference constraint violations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper describes a compactor that is practical for compacting whole chips that are designed hierarchically, and can produce a reasonable result in spite of the layout being over-constrained. The layout produced is good enough to be used in high volume chips. The compactor is currently used in a cell layout system and a chip assembly tool.