Floss: An approach to automated layout for high-volume designs
DAC '77 Proceedings of the 14th Design Automation Conference
An analytical method for compacting routing area in integrated circuits
DAC '82 Proceedings of the 19th Design Automation Conference
ALI: A procedural language to describe VLSI layouts
DAC '82 Proceedings of the 19th Design Automation Conference
Geometrical compaction in one dimension for channel routing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Layout compaction with attractive and repulsive constraints
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
An efficient methodology for symbolic compaction of analog IC's with multiple symmetry constraints
EURO-DAC '92 Proceedings of the conference on European design automation
CELLERITY: a fully automatic layout synthesis system for standard cell libraries
DAC '97 Proceedings of the 34th annual Design Automation Conference
Symbolic layout compaction review
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Compaction with incremental over-constraint resolution
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A subjective review of compaction (tutorial session)
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Symbolic hierarchical artwork generation system
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Minplex—a compactor that minimizes the bounding rectangle and individual rectangles in a layout
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A hiererachical, error-tolerant compactor
DAC '84 Proceedings of the 21st Design Automation Conference
IBM Journal of Research and Development
| Hi-index | 0.00 |
The compaction of IC or hybrid layouts by means of the “longest path” method yields a slack in the placement of part of the elements, which, in its turn, can be used to reduce the overall wire-length. The result is an improved electrical performance and a smaller layout. The optimization problem was transformed to a graphtheoretical problem in a way similar to the compaction problem itself. Our procedure starts by adding pieces of information out of the connectivity of the layout to the constraint graph. The succeeding heuristic algorithms generate a new tree of longest paths, taking the linear inequalities and the result of the longest path calculation into consideration. A few examples demonstrate the significant reduction of wire-length and sometimes even an additional reduction of layout area achieved with low computational effort.