A subjective review of compaction (tutorial session)
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Improved compaction by minimized length of wires
DAC '83 Proceedings of the 20th Design Automation Conference
A hiererachical, error-tolerant compactor
DAC '84 Proceedings of the 21st Design Automation Conference
Technology tracking of non manhattan VLSI layout
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
PALACE: a layout generator for SCVS logic blocks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A new approach to hierarchical adaptation using sequence-control based on cell interactions
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
MSTC: a method for identifying overconstraints during hierarchical compaction
DAC '93 Proceedings of the 30th international Design Automation Conference
Efficient algorithms for debugging timing constraint violations
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Proceedings of the tenth international symposium on Hardware/software codesign
Provably efficient algorithms for resolving temporal and spatial difference constraint violations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The occurrence and resolution of over-constraints in one-dimensional layout compaction will be discussed. A new algorithm is given which solves the longest path problem in the constraint graph and resolves all positive cycles either by constraint relaxation or by jog generation. The presented algorithm eliminates the positive cycles one at a time and reuses the intermediate results, which had been obtained up to the point when the cycle was detected. Thus, the amount of additional effort required for the over-constraint resolution is very low. Some typical over-constrained situations and their solutions are shown. The algorithm has been implemented in a mask compaction program that is currently in use for process migration and design rule error correction at SIEMENS. CPU-times gained during the process migration of a microcontroller layout are given.