Safety analysis of timing properties in real-time systems
IEEE Transactions on Software Engineering - Special issue on reliability and safety in real-time process control
Introduction to algorithms
Artificial Intelligence - Special issue on knowledge representation
A fast and effective heuristic for the feedback arc set problem
Information Processing Letters
Software scheduling in the co-synthesis of reactive real-time systems
DAC '94 Proceedings of the 31st annual Design Automation Conference
Scheduling using behavioral templates
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An efficient graph algorithm for FSM scheduling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Compaction with incremental over-constraint resolution
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Rate analysis for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Shortest paths algorithms: theory and experimental evaluation
SODA '94 Proceedings of the fifth annual ACM-SIAM symposium on Discrete algorithms
A constraint-based application model and scheduling techniques for power-aware systems
Proceedings of the ninth international symposium on Hardware/software codesign
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Negative-Cycle Detection Algorithms
ESA '96 Proceedings of the Fourth Annual European Symposium on Algorithms
A hiererachical, error-tolerant compactor
DAC '84 Proceedings of the 21st Design Automation Conference
The MSP.RTL real-time scheduler synthesis tool
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Timing Analysis of Embedded Real-Time Systems
Timing Analysis of Embedded Real-Time Systems
Resource-Constrained Algebraic Transformation for Loop Pipelining
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Faster maximum and minimum mean cycle algorithms for system-performance analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient algorithms for debugging timing constraint violations
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Experimental analysis of the fastest optimum cycle ratio and mean algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Provably efficient algorithms for resolving temporal and spatial difference constraint violations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Feasibility of semiring-based timing constraints
ACM Transactions on Embedded Computing Systems (TECS)
A Metric for Quantifying Similarity between Timing Constraint Sets in Real-Time Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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A system of binary linear constraints or difference constraints (SDC) contains a set of variables that are constrained by a set of unary or binary linear inequalities. In such diverse applications as scheduling, interface timing verification, real-time systems, multimedia systems, layout compaction, and constraint satisfaction, SDCs have successfully been used to model systems of both temporal and spatial constraints. Formally, SDCs are modeled by weighted, directed (constraint) graphs. The consistency of an SDC means that there is at least one instantiation of its variables that satisfies all its constraints. It is well known that the absence of positive cycles in a graph implies the consistency of the corresponding SDC, so the consistency can be decided in strongly polynomial time. If a SDC is found to be inconsistent, it has to be repaired to make it consistent. This task is equivalent to removing positive cycles from the corresponding graph. All the previous algorithms for this task take time proportional to the number of positive cycles in the graph, which can grow exponentially. In this paper, we propose a strongly polynomial-time algorithm, i.e., an algorithm whose time complexity is polynomial in the size of the graph. Our algorithm takes in a graph and returns a list of edges and the changes in their weights to remove all the positive cycles from the graph. We experimentally quantify the length of the edge list and the running time of the algorithm on large benchmark graphs. We show that both are very small, so our algorithm is practical.