Efficient algorithms for debugging timing constraint violations
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Proceedings of the tenth international symposium on Hardware/software codesign
Feasibility of semiring-based timing constraints
ACM Transactions on Embedded Computing Systems (TECS)
A Metric for Quantifying Similarity between Timing Constraint Sets in Real-Time Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We address the problem of timing constraint derivation and validation for reactive and real-time embedded systems. We assume that such a system is structured into its tasks, and the structure is modeled using a task graph. Our solution uses the timing behavior committed by the environment to the system first to derive the timing constraints on the system''s internal behavior and then use them to derive and validate the timing constraints on the system''s external behavior. Our solution consists of the following contributions: (1) a generalized task graph model and a comprehensive classification of timing constraints, (2) algorithms for derivation and validation of timing constraints of the system modeled in the generalized task graph model, (3) new and improved algorithms for finding the performance of cyclic embedded systems and a comprehensive comparison of the existing algorithms, (4) a general formulation of the problem of debugging timing violations in cyclic embedded systems and its complexity, and (5) a codesign methodology that combines the model and the algorithms, and its implementation in a tool called RADHA-RATAN. The main advantages of our solution are that it simplifies the problem of ensuring timing correctness of the system by reducing the complexity of the problem from system level to task level, and that it makes the codesign methodology timing-driven in that our solution makes it possible to maintain a handle on the system''s timing correctness from very early stages in the system''s design flow.