Safety analysis of timing properties in real-time systems
IEEE Transactions on Software Engineering - Special issue on reliability and safety in real-time process control
Introduction to algorithms
Artificial Intelligence - Special issue on knowledge representation
A fast and effective heuristic for the feedback arc set problem
Information Processing Letters
Software scheduling in the co-synthesis of reactive real-time systems
DAC '94 Proceedings of the 31st annual Design Automation Conference
Scheduling using behavioral templates
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An efficient graph algorithm for FSM scheduling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Compaction with incremental over-constraint resolution
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Rate analysis for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Shortest paths algorithms: theory and experimental evaluation
SODA '94 Proceedings of the fifth annual ACM-SIAM symposium on Discrete algorithms
A constraint-based application model and scheduling techniques for power-aware systems
Proceedings of the ninth international symposium on Hardware/software codesign
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Negative-Cycle Detection Algorithms
ESA '96 Proceedings of the Fourth Annual European Symposium on Algorithms
Proceedings of the tenth international symposium on Hardware/software codesign
A hiererachical, error-tolerant compactor
DAC '84 Proceedings of the 21st Design Automation Conference
The MSP.RTL real-time scheduler synthesis tool
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Timing Analysis of Embedded Real-Time Systems
Timing Analysis of Embedded Real-Time Systems
Resource-Constrained Algebraic Transformation for Loop Pipelining
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Faster maximum and minimum mean cycle algorithms for system-performance analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic Debugging of Real-Time Systems Based on Incremental Satisfiability Counting
IEEE Transactions on Computers
Provably efficient algorithms for resolving temporal and spatial difference constraint violations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Feasibility of semiring-based timing constraints
ACM Transactions on Embedded Computing Systems (TECS)
A Metric for Quantifying Similarity between Timing Constraint Sets in Real-Time Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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A system of binary linear constraints or difference constraints (SDC) consists of a set of variables that are constrained by a set of unary or binary linear inequalities. In such diverse applications as scheduling, interface timing verification, real-time systems, multimedia systems, layout compaction, and constraint satisfaction, SDCs have successfully been used to model systems of both temporal and spatial constraints. Formally, an SDC is modeled by a weighted, directed graph called a constraint graph. The consistency (or feasibility) of an SDC means that there is at least one instantiation (or solution) of its variables that satisfies all its constraints. It is well known that the absence of positive cycles in a constraint graph implies the consistency of the corresponding SDC, so the consistency can be decided in strongly polynomial time. If the system is consistent, a solution can also be found in strongly polynomial time. However, if the system is inconsistent, there is no solution unless the system is repaired (or debugged). The debugging task is equivalent to freeing the corresponding constraint graph from all its positive cycles. All the previous algorithms for this task take time proportional to the number of positive cycles in the graph, which can grow exponentially. We have recently proposed a provably strongly polynomial-time algorithm for this task, i.e., an algorithm whose time complexity is polynomial in the size of the input constraint graph. In this paper, we propose extensions of this algorithm for different debugging scenarios. We theoretically and experimentally justify the efficiency and efficacy of our algorithms.